The SCL8138 is a high-speed Si-gate CMOS device implemented in Low power Schottky TTL(LSTTL). The chip is in compliance with JEDEC standard no. 7A. The SCL8138 decoders and can accept three address inputs (A0, A1, A2) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0/ toY7/) and 8 open drain outputs (C0/ to C7/).
SCL8138 is designed for systems applications of LED driver & is intended for ghost effect elimination. When any channel is turned off, the corresponding Cx will discharge the PMOS drain node to one reference level, which is lower than LED turn on voltage.
SCL8138 also features dead-time monitoring threshold 40ms for decoder input switching. If no switching is detected over 40ms decoder outputs will all be disabled.
The “138” features three enable inputs: two active LOW (E1/ and E2/) and one active HIGH (E3). Every output will be HIGH unless E1/ and E2/ are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the “138” to a 1-of-32 (5 lines to 32 lines) decoder with just four “138” ICs and one inverter. The ”138” can be used as an eight output de-multiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. |
